© Dave Jones
© Dave Jones

TUT design computer chip

A research group at the Tallinn University of Technology (TUT), Estonia, has designed an innovative digital computer chip that can localise all of its faults and inform the external environment.

According to the head of the research group, Professor at the Department of Computer Engineering, Jaan Raik, an explosive increase in the number of faults caused by the ever-decreasing size of chips makes it a particularly topical issue.

The digital chip was designed as a result of several master’s theses, the supervisors of which included PhD students and researchers from TUT.

Work began in October 2015. The student project was led by TUT’s PhD student Siavoosh Payandeh Azad from Iran, who defended his master’s degree at the KTH Royal Institute of Technology, Sweden.

The technology applied in the computer chip has been developed under the European Union’s Horizon 2020 research project IMMORTAL.

The project will be led by TUT and combines the expertise of the International Business Machines (IBM) Corporation, German Aerospace Centre (DLR), Estonian company Testonica Lab OÜ and several international universities investigating solutions for managing faults in complex computer systems.

Raik said: “It must be noted, as an indication of consistency, that the previous digital chip produced by an Estonian university was manufactured 20 years ago in the same institute and this was a cryptoprocessor designed by Jüri Põldre.

“Miniaturisation of chip technology has advanced at a dizzying pace in the last few decades. Back then, the technology used was 30 to 40 times more primitive and clumsy compared to today’s technology.”