Quicker, cheaper chip testing
A team of EU-funded researchers have developed a way of reducing the cost and length of time in the testing of computer microchips. It’s hoped the new process will increase chip production whilst lowering the cost of electronic equipment and devices.
Scientists working on the FP7 ‘DIAMOND’ project developed an ‘holistic’ approach which could help reduce the cost of developing chips by €15m. The scientists developed the ‘Formal repair environment for simple C’ (Forensic), an open source system-level design error localisation and correction system.
In comments carried on the European Commission’s website, Dr Jaan Raik of the Tallinn University of Technology, which led the research, said: “First, an holistic model for different types of faults was developed. Based on this model the same localisation engines can be applied to design errors, soft errors and defects.
“Second, more efficient automated localisation and correction methods were developed. Particular stress was put on system-level approaches where previous research work has been inadequate. And third, post-silicon in situ debug approaches were developed. Such approaches extend the lifetime of silicon chips by localising and isolating faulty regions in them”.
As a result of the project, its hoped the lab-to-market time could be reduced, helping increase the speed of innovation, whilst decreasing cost; IBM has already filed for two patents following the new technological development. The project ran between 2010 and 2012 and received €2.9m in EU funding.
